Test Sequence Generation of Random Single Input Change (RSIC) Based on Counter
نویسنده
چکیده
In any VLSI circuit, power consumption is very important factor that should be taken into consideration. Generally, dynamic power consumption is more dominant when compared to that of static. To reduce the internal switching activity rate of the circuit under test (CUT), we can recombine testing vector to raise the correlation between testing vector. Random Single Input Change (RSIC) test theory is proposed, which optimize the switching activity of circuit-under-test and then result in decrease of test power consumption. It is suitable for BIST of digital VLSI especially. The proposed circuit is simulated in DSCH and CadenceVirtuso. The results obtained in various tools are presented in
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